The device described herein is intended to satisfy the requirements of high performance bipolar transistors. These requirements include base widths on the order of 600 .ANG. self-aligned emitter and base contacts, and minimized parasitic capacitances. In addition, future bipolar transistors are expected to make increasing use of epitaxial techniques to improve the vertical profile. They also require a linkup with a minimal extrinsic base diffusion area to reduce the base-collector capacitance (C.sub.bc) and base resistance (R.sub.b). Other bipolar structures, such as the SELECT (Self-Aligned Edge Contact Technology) structure described in the article by Washio et al., published at the IEEE International Solid State Conference held on Feb. 25, 1987, have been devised to achieve similar goals, however, the present invention illustrates a unique and advantageous structure along with a unique and advantageous method of manufacturing such structures.
The SELECT structure is a species of SICOS (Sidewall Base Contact Structure) which is described in the article by Nakamura, et al., at pages 472-475 of IEDM, 1986.
However, SICOS based transistors suffer from processing problems. For example, the pad oxide between the extrinsic base polysilicon and collector, P substrate, is a fully thermal oxide. Because the subcollector of a SICOS transistor is patterned, the use of a fully thermal oxide will lead to thickness discrepancies between the thickness of the oxide located over the P substrate and the thickness of the oxide located over N+ subcollector, with the latter being as much as a factor of 2 thicker than the former. Therefore, there will be an increase in the extrinsic base P substrate capacitance.
In the SICOS structure, a LOCOS (Local Oxidation of Silicon as described in "Local Oxidation of Silicon and its Application in Semiconductor Device Technology," by J. A. Appels, E. Kooi, M. M. Paffen, J. J. H. Schatorje, and W. H. C. G. Verkuylen in Philips Res. Rep., Vol. 25, p. 118, 1970) scheme is used to isolate the N collector from the extrinsic base polysilicon. In this scheme, a nitride layer is deposited on a thin pad oxide and patterned. A subsequent thermal oxidation forms the field oxide along with regions known in the art as a birds head and a birds beak. Prior to deposition of the extrinsic base polysilicon, the nitride/oxide is removed from the sides of the pedestal. The oxide must be "dipped" off in BHF (Buffered Hydrofluoric Acid). During this etch, due to the tapered birds beak, the exact position of the oxide/silicon boundary is not accurately known. Consequently, to ensure contact, there must be an excessive dip and a resultant "deep" extrinsic base contact on the side of the silicon pedestal. This has two undesired consequences. First, it expands the area of the extrinsic base/collector contact, increasing the capacitance of the device. Second, all high performance transistors require an increased collector concentration under the base. The implant must be patterned inside of the silicon pedestal to prevent a P+ extrinsic base/N collector implant junction from being formed. Failure to do this would increase the extrinsic base/collector capacitance and decrease the breakdown voltage of the transistor. Besides these processing problems, the structure is not fully self-aligned. In later versions of SICOS, as described by K. Washio et al. in "Fabrication Process and Device Characteristics of Sidewall Base Contact Structure Transistor Using Two-Step Oxidation of Sidewall Surface," IEEE Transactions on Elect. Devices, Vol. 35, No. 10, pp. 1596-1600 (October 1988), some of the processing problems were addressed but the structure is still not fully self-aligned.
A new, fully self-aligned device referred to as SDX has recently been described by Y. Yamamoto in IEEE Transactions on Elect. Devices, Vol. 35, No. 10, pp. 1601-1608 (1988). This process uses the diffusion of boron from the shallow trench oxide to self-align the extrinsic base contact. However, this process takes place at 900.degree. C. for 30 minutes. This step will drive in a P++ diffusion deep into the pedestal and increase the base collector capacitance.
In U.S. Pat. No. 4,679,305 to Morizuka, a self-aligned GaAs bipolar transistor is described. In that device, the extrinsic base region is implanted before the self-aligned isolation region. Implantation of the extrinsic base early in the process in silicon technology would result in excessive vertical (deep junction) and lateral (emitter/base leakage) diffusion when subjected to the heat cycle of an integrated process. In addition, in that GaAs device, the isolation regions are formed by ion implantation, a technique which is not adaptable to silicon technology. In comparison, in the present invention the resulting structure is substantially improved by eliminating the interface between the extrinsic base and the emitter. In addition, the present invention provides a substantial reduction in the collector-to-extrinsic-base interface. Finally, the manufacturing process is simplified by eliminating at least one of the multiple sidewalls required to construct the Morizuka device.